Resonators Required In Traditional High-Performance VCSOs

Digitally-controlled oscillator (DCO) Recently, integrated circuit (IC) designers have started taking advantage of high-density, high-speed CMOS technology to develop digital signal processing (DSP) intensive clock source solutions that are both high performance and frequency agile. These DSP-based architectures use a low frequency resonator element (typically a quartz crystal) and a high-frequency on-chip VCO to produce a frequency agile high-speed, low-jitter output clock whose output rate is digitally-controlled and whose jitter performance equals that of traditional high-performance VCSOs. The resolution of the digital frequency control can be very fine, much less than one ppm, with a continuous tuning range of more than one GHz. Compared to the high frequency (>100 MHz), high absolute accuracy (<±20 ppm) and pulled (±20-100 ppm) resonators required in traditional high-performance VCSOs, these resonators can be very small and inexpensive because the reference resonator is low frequency (<40 MHz), has loose absolute frequency accuracy requirements (<±10,000 ppm) and is not pulled with changes in DCO
output frequency. These resonators can be very small and inexpensive.

New DSP enhanced PLL architecture
Utilizing the digital control interface provided by the DCO, a fully integrated digital PLL becomes possible that takes advantage of digital signal processing (DSP) algorithms

In this DSP-based PLL architecture, the phase detector output is converted to digital format by a high-speed analog to digital converter (ADC). Following the ADC, all signal processing is done in the digital domain using high-speed DSP algorithms. The wide tuning range of the DCO (~15%) when combined with high-performance output dividers enables one PLL design to support a wide range of clock multiplication factors that would normally require multiple VCSO-based PLLs. In addition, the phase-noise performance of the silicon-based DCO is equivalent to that of fixed frequency VCSO alternatives, enabling narrowband loop operation for applications requiring jitter attenuation. The relative phase-noise performance of VCSO-based clock multiplier hybrids and a fully integrated DCO-based clock multiplier. The biggest difference can be seen at high frequencies where the lower thermal noise of CMOS PLL yields improved jitter performance compared to the hybrid approaches.

Integration of the PLL into a sub-micron CMOS process technology enables new digitally-controlled features such as hitless switching, clock multiplication, skew control and jitter attenuation. Digitally-controlled hitless switching virtually eliminates the output clock phase transient normally associated with switching the PLL input
clock between two asynchronous clock sources, a function required in many optical port card architectures. This approach eliminates a cascade of narrow bandwidth PLLs that have traditionally been used to control phase transients during a clock switch. Programmable clock multiplication supports integer as well as non-integer scaling
ratios, simplifying the translation to FEC frequencies or the translation between datacom and telecom data rates. Fine skew control allows adjustment of the input-to-output clock phase in picosecond increments, and digital bandwidth control allows static or dynamic modification of the PLL loop bandwidth in order to enhance PLL
locking behavior and increase filtering of incoming clock jitter. These new DSP-based PLLs enable radical modifications in the system timing architecture for line cards providing multi-rate, multi-protocol support and also enabling improved test capability.

Silicon Labs - 8051 Microcontroller and Programmable Clock IC